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Wafer Scale Integration of Double Gated WS2 Transistors in 300 mm Si CMOS Fab

I. Asselberghs, Q. Smets, T. Schram, B. Groven, D. Verreck, A. Afzalian, G. Arutchelvan, A. Gaur, D. Cott, T. Maurice, S. Brems, K. Kennes, A. Phommahaxay, E. Dupuy, D. Radisic, J-F de Marneffe, A. Thiam, W. Li, K. Devriendt, C. Huyghebaert, D. Lin, M. Caymax, P. Morin, I.P. Radu

DOI
10.17023/0hbw-bd90
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