Skip to main content

lin

Showing 1 - 8 of 8 resources. Too many results? Use the search filters to refine your search.
Sort by
Sub-0.5 nm Interfacial Dielectric Enables Superior Electrostatics: 65 mV/dec Top-Gated Carbon Nanotube FETs at 15 nm Gate Length
15 Dec 2020

Sub-0.5 nm Interfacial Dielectric Enables Superior Electrostatics: 65 mV/dec Top-Gated Carbon Nanotube FETs at 15 nm Gate Length

  • EDS
    Members: $5.00
    IEEE Members: $10.00
    Non-members: $20.00
3D Integration of Vertical Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers
15 Dec 2020

3D Integration of Vertical Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers

  • EDS
    Members: $5.00
    IEEE Members: $10.00
    Non-members: $20.00
A Reliability Enhanced 5 nm CMOS Technology Featuring 5th Generation FinFET with Fully Developed EUV and High Mobility Channel for Mobile SoC and High Performance COmputing Application
15 Dec 2020

A Reliability Enhanced 5 nm CMOS Technology Featuring 5th Generation FinFET with Fully Developed EUV and High Mobility Channel for Mobile SoC and High Performance COmputing Application

  • EDS
    Members: $5.00
    IEEE Members: $10.00
    Non-members: $20.00
Plasmonics - Breaking the Barriers of Silicon Photonics for High-Performance Chip to Chip Interconnects
15 Dec 2020

Plasmonics - Breaking the Barriers of Silicon Photonics for High-Performance Chip to Chip Interconnects

  • EDS
    Members: $5.00
    IEEE Members: $10.00
    Non-members: $20.00
First Demonstration of Heterogeneous Complemntary FETs Utilizing Low Temperature (200 C) Hetero Layers Bonding Technique (LT-HBT)
15 Dec 2020

First Demonstration of Heterogeneous Complemntary FETs Utilizing Low Temperature (200 C) Hetero Layers Bonding Technique (LT-HBT)

  • EDS
    Members: $5.00
    IEEE Members: $10.00
    Non-members: $20.00
Staggered Metallization with Air Gaps for Independently Tuned Interconnect Resistance and Capacitance
15 Dec 2020

Staggered Metallization with Air Gaps for Independently Tuned Interconnect Resistance and Capacitance

  • EDS
    Members: $5.00
    IEEE Members: $10.00
    Non-members: $20.00
Wafer Scale Integration of Double Gated WS2 Transistors in 300 mm Si CMOS Fab
15 Dec 2020

Wafer Scale Integration of Double Gated WS2 Transistors in 300 mm Si CMOS Fab

  • EDS
    Members: $5.00
    IEEE Members: $10.00
    Non-members: $20.00
DTCO Launches Moore''s Law Over the Feature Scaling Wall
15 Dec 2020

DTCO Launches Moore''s Law Over the Feature Scaling Wall

  • EDS
    Members: $5.00
    IEEE Members: $10.00
    Non-members: $20.00